Through Silicon Vias - Nexlogic

Through Silicon Vias

While bumping and RDL may reduce the surface area chips use on a circuit board, space usage can be even more efficient when chips are stacked. Stacking is a strategy which improves the electrical performance of multiple chips. Wire bonding is one way to create stacked assemblies, and silicon vias (TSVs) have emerged as an attractive alternative that can offer a smaller form factor. A TSV is an electrical connection through the entire thickness of the chip, creating the shortest possible path from one side of the chip to the other.

In TSVs, the vias (holes) are etched from the front side of the wafer to a certain depth. These are then isolated and filled by depositing a conductive material, typically copper. After chip fabrication is complete, the wafer is thinned from the back side to expose the vias, and metal is deposited on the backside of the wafer to complete the TSV interconnection.

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