Packaging Design Options
There are a number of IC packages available, which includes wire bond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). Interconnects are used to connect one die to another one in packages. TSVs have the highest I/O counts, followed by WLP, flip-chip and wire bond.
Wire bonding is the most common packaging type. A wire bonder stitches one chip to another chip or substrate using tiny wires which could be of different metals as well as different thickness. Wire bonding is used for commodity packages and memory die stacking. There could be single row wire bonding as well as staggered wire bonding consisting of 3, 4 and up to 5 stacks, if the package density is high.
In flip-chip technique, there are either larger solder bumps, or tiny copper bumps as well as copper pillars, which are formed on top of a chip using various process steps. The device is then flipped and mounted on a separate die, board or a substrate. The bumps land on copper pads, forming an electrical connection. The dies are then bonded using a system called a wafer bonder.
WLP (Wafer-level packaging) packages the dies while on a wafer. WLP enables smaller two-dimensional connections that redistribute the output of the silicon die to a greater area, enabling higher I/O density, higher bandwidth and higher performance for modern devices.
NexLogic can perform wire bonding, flip chip or WLP package design and turnkey manufacturing including wafer design and manufacturing through her foundry partners in Asia.