Via in Pads and BGA - Nexlogic

Via in Pads and BGA

via-padsIn PCB design, via refers to a pad with a plated hole that connects copper tracks from one layer of the board to other layer(s). High-density multi-layer PCBs may have blind vias, which are visible only on one surface, or buried vias, which are visible on neither, normally referred to as micro vias. The advent and extensive use of finer pitch devices and requirements for smaller size PCBs creates new challenges. An exciting solution to these challenges uses a recent, but common PCB manufacturing technology with self descriptive name, “via in pad”.

Via in pad helps to reduce inductance, increase density and employ finer pitch array packages. The via in pad approach places a via directly under the device’s contact pads. This allows higher component density and improved routing. Consequently, via in pad provides the designer significant PCB space savings. For example, traditional fan-out places four components, whereas with via in pad, six components can be placed within the same board outline.

Filled via in pad is a way to achieve intermediate density with an intermediate cost compared to using blind/buried vias. Some of the key advantages associated with using the via in pad technology are:

  • Fan out fine pitch (less than .75mm) BGAs
  • Meets closely packed placement requirements
  • Better thermal management
  • Overcomes high speed design issues and constraints i.e. low inductance
  • No via plugging is required at component locations
  • Provides a flat, coplanar surface for component attachment

However, there are some disadvantages associated with this technology. The most prominent and worrisome is the cost impact associated with adopting a new technology. PCB vendors identified two primary cost drivers associated with specifying via in pad technology: Additional manufacturing process complexity and the underlying material cost for the conductive fill.

Specifically, via in pad technology adds eight to 10 steps to the board manufacturing process while via fill cost is a function of the via size and actual number of via instances on any given design. However, the reduction in layer count realized by using via in pad technology compensates for the added cost associated with this process.

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