Underfill - NexLogic Technologies


These days, micro CSP, micro BGA, QFN, and wafer level packaging (WLF) must meet growing requirements. Those include greater chip functionality, reduced size, tough mechanical and high reliability requirements, as well as greater stress relaxation for thermal stress and extremely short solder joints.

Figure 3_Using top layersThis is where underfill comes in to satisfactorily deal with those emerging challenges at PCB assembly. Fig. 1 shows a typical underfill process for a micro BGA. Underfill provides extra rigidity; allows the end product to satisfactorily resist thermal stress caused by heat cycles, severe physical stress caused by mechanical shock and bending, as well as, large thermal expansion mismatching. Thanks to this underfill, stress is dissipated throughout the device’s package, and the concentration of stress on the roots of the solder balls is avoided.

Basically, underfill encapsulates the bottom side of the silicon chip. The term “encapsulates” in PCB assembly terms usually means covering the top surface of a device where fragile interconnects are located. But in the case of underfill, it is loosely used to describe how the fragile interconnects between the chip’s bottom side and the PCB’s topside are covered. Mounting conventional CSP and BGA packaging onto the board using conventional assembly steps and techniques usually produce sound mechanical and thermal properties.

The applications are rugged environments, hostile atmosphere or toxic gases where the boards are used.

But in the case where there’s a combination of micro CSPs, micro BGAs and an extremely high reliability requirement, there can be a possibility that certain harsh environmental forces may deal a particular blow to a device’s solder bonds, creating faulty or non-existent solder connections.

Once underfill is applied, however, those package and board connections can be strengthened considerably by upwards of 10 times. Therefore, the underfill process dramatically enhances thermal cycling performance and shock resistance of those chip packaging and board connections.

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