Signal integrity demands considerable attention due to the increasing complexity of PCB designs and the highly advanced digital and analog components OEM system houses require. There are countless areas a PCB layout engineer can overlook, thus creating signal integrity issues
One especially important aspect is proper decoupling capacitors for BGA consideration. It is recommended that decoupling caps be placed right on the opposite side of the BGA right below the pin itself, Fig. 1. Therefore, BGAs will be fanned out with a via that is on the pad. It’s filled either with a conductive or non-conductive filling.
Some manufacturers recommend the use of a non-conductive filling because it provides a surface that is more flat after the plating. Vias are placed shut and have a flat finish on the topside. At the opposite side of the BGA, on the bottom side, are the decoupling caps. This provides a low inductance path from the BGA to the power system.
Also, if an FPGA is used in this high-speed design, I/O optimization is necessary before routing is started. This option can be considered either in the layout or in the schematic. That is to optimize those signals since most of those data pins are pin swappable. The schematic designer can switch those I/Os, and once the net list is re-imported, a cleaner view of the rat’s nest can be achieved. Consequently, routing becomes simpler and clean once those signals are routed.