Get The Latest On DFM Issues - Nexlogic
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You’ve probably heard it a million times. That is PCB design/layout engineers must communicate with assembly and manufacturing engineering. Easy to say, but in many case, it’s hard, especially when you’re working with separate PCB design and assembly houses. And also, DFM is often neglected for any number of reasons.

What is worse is that in some instances PCB design/layout engineers can easily overlook key factors that at first glance don’t appear significant. Later on, however, they play a major role during manufacturing and are the root cause of poor yields.

You have to consider that today’s PCB designs are challenging and daunting to numbers of inexperienced designers. Plus, today’s high-speed designs and highly advanced packaging and board technologies are a recipe for creating problematic boards.

Fig 1 TombstoneA case in point is when a designer decides to reduce the pad size to match trace width. However, in this case, it was reduced so much that this particular PCB design incurred a number of issues in manufacturing and in particular, tombstoning, Fig. 1. Together with other design-for-manufacturing (DFM) issues, they caused yields below 60 percent when the target was expected to be above 90 percent.

In this day and age, it’s a good idea for the OEM to take a closer look at DFM for their PCB projects. To learn more about more recent DFM issues, check out our article in EE Times.

Meanwhile, here are some tips and hints to guide you along the way to assure a more effective DFM for your PCB projects.

  • In theory, the same trace width as pad size may be correct. But in practice manufacturing issues can arise, especially when traces and pads are exceedingly small.
  • Sometimes in high-speed designs, larger 15 mil vias should be smaller, like 8 mils to avoid solder from going down the barrel and causing shorts on peripheral pads.
  • In high-speed designs, care must be taken to avoid insufficient solder mask between two pads.
  • A number of DFM issues arise due to PCB layout errors. Areas of concern include pad definition, component footprint, layer stack-up, material selection, fan out, trace clearance, and others.
  • The PCB designer must be diligent to assure the right and uniform stack up to avoid board warping.
  • Warping occurs due to acute angle traces where acid traps occur. If that chemical isn’t cleaned away, it can eat away at the traces even after assembly to cause intermittent connections.

Using via-in-pads for BGAs is another area the PCB layout designer must be careful about. Via-in-pad is widely popular, especially for finer pitch BGAs below 0.75mm. Compared with dog-bone fan outs, via-in-pad increases density and allows the use of finer pitch packages. Also, decoupling capacitors can be placed directly over the vias on the opposite side of the BGA, thus reducing intrinsic inductance.

While there are advantages to using via-in-pad, there are also issues. The most prevalent issue is when using via-in-pad, conductive and non-conductive material is used to fill the vias and then plated over.

If the fab house isn’t knowledgeable with this process, a number of issues can occur like moisture entrapment, which wreaks havoc at assembly. When moisture is trapped, vias and pads can be popped and dimples are caused during reflow and that can destroy BGA pads. Using non-conductive via fillings is a workaround and a tradeoff when using via-in-pad. These days, this is a popular approach as a way to avoid extensive expansion or contraction, which basically reduces moisture entrapment.