Get Ready for DDR4 - Nexlogic
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In a few months, the probability of your PCB projects using next generation DDR4 SDRAMs is high. To avoid time consuming issues or technical glitches, prudent OEMs will seek PCB designers who have in-depth experience successfully designing with and routing the earlier generations, DDR2 and DDR3.

Two major differences between DDR4 and DDR3 is DDR4’s lower power consumption and higher speed. Spurred on by a new point-to-point architecture, DDR4 will likely consume less power, probably 30 to 40 percent less than DDR3 since DDR4 will run at 1.2 volts versus DDR3, which runs at 1.5 volts. Secondly, DDR4 will be about 1.7 times faster than DDR3. It’ll be running at a maximum of 3200 Mbps or double the speed of DDR3. Also, DDR4 packaging will have 284 pins versus the 240 pins for DDR3.

ddr3-pcb-layoutDDR4’s point-to-point architecture delivers better timing margins, handing the PCB designer more tolerances to work with when performing the routing and length matching the different bits, clock, and address lines. In length matching, the important item is the difference of the signal lengths within a given byte lane to its strobe. So for DQS (Data Queue Strobe) and DM (Data Mask) lines maximum deviation is to be ±/10 picoseconds.

Translated into length, that’s around ±/50 mils on a PCB’s FR4 material. This doesn’t allow much leeway when length matching the signals. For many PCB designers, this is a challenge, especially working within tight spaces. The more cramped the space, the more difficult it is to match those lengths. Fig. 1 shows length matching for a DDR3 PCB layout.

You can get a more in-depth perspective about DDR3 and DDR4 PCB routing by reading our most recent article appearing in EE Times/

Meanwhile, here are some tips to get you better acquainted with DDR3-DDR4 routing and prepare you for next generation designs.

  • Reference voltage or Vref continues to gain greater importance and the PCB designer should treat it accordingly, especially guarding Vref from noisy signals like clocks.
  • Filtering noise is equally as important and Vref should be decoupled with a 0.1 microfarad (µF) capacitor very close to the power pin.
  • Vref pseudo-open drain or POD should be a low inductance signal or “thick” signal. It should be routed thicker than other signals, typicaly 20 to 25 mils.
  • A good reference plane must be provided to Vref and all other signals including DDR bits and command, control, at address lines, and clocks.
  • PCB designer must understand the significance of properly terminating address, command, control lines and clock signals.
  • Assurances must be made that all lines are testable, whether they are byte lanes, address lines, command, control, clocks.

For DDR4, a pseudo-open drain or POD I/O architecture will be used. This is different from the traditional multi-drop bus interface used for previous DDRs. It offers more relaxed timing margins with even less power consumption than DDR 3. It helps the PCB by allowing relaxed rules for the same transfer rates versus the earlier DDR3 ones.

Improved transfer rate, data rates, and speeds are expected going from DDR3 to DDR4. Essentially, what it comes down to is routing guidelines will be the same for DDR4 as DDR3. However, the memory interface will be more efficient, more powerful, and will have a much better data rate like about 1.7 times faster than DDR3 with the same routing rules.