You can say PCB layout and test are inseparable; they go together under the same roof to assure product reliability. Sometimes, OEMs take a big gamble by opting to take their PCB projects to one design layout house and then have those boards tested by another shop. Therefore, it is of utmost importance for the OEM to ensure that boards are designed to be testable by maximizing in-circuit testing (ICT) coverage and capability, as shown in the figure below. There are a number of design-for-test (DFT) considerations and techniques demanded of the savvy PCB layout engineer, plus that experienced individual must work hand in hand with his or her in-house test engineering staff.
With growing numbers of new PCB designs being populated with BGAs, it is important to place test points away from BGA components to reduce BGA solder stress and board flex. If probing under BGA is needed, the number of points should be limited and shouldn’t be in excess of 29 test-point/square inch with 5.5 to 6.5 oz probe, and 47 test-point/square inch with 4 oz probe.
Other important tips include:
- If possible, place test points for each node on one side of the board (Secondary side preferred.) This reduces the fixture and maintenance cost. Top side probing is less accurate than bottom side probing.
- Use boundary-scan compliant devices when possible. This provides some accessibility to the devices via boundary scan for the board with limited access test points. Also, chain the multiple JTAG devices.
- Don’t tie IC control lines directly to power or ground. Add pull-up or pull-down resistors. This allows the in-circuit tester to control these lines when required during IC testing.
- Have a test point for all electrical nodes, including unused IC pins. This allows for detection of internal and external shorts.
- Oscillator should be gated with logic circuit allowing ICT to disable the clock signal as needed during IC testing.
- To measure a low ohm resistor, two test points on each side of the component may be required to support 4-wire Kelvin resistance measuring.
Regardless of the type or shape, preferred test points should always be greater than 0.030î flat to flat or diameter and 0.040î for topside targets. Pad sizes as small as 0.018î in diameter can still be probed with higher fixture cost. If test vias are used, the minimum inside diameter of the plated through-hole should be 0.018î.
Test point locations should be distributed as evenly as possible over the board. A high density of test points or clusters should be avoided. Consider component-free areas on the opposite side of the PCB to allow for counter-force support such as pushdown finger or block.