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Printed Circuit Design & Fab: Characteristics of a Third-Level PCB Assembly

By and large, PCB assembly up to now has been rather traditional. Surface mount technology has made significant inroads to account for the greater majority of assembly technology compared to through-hole. However, these days PCB assembly takes on new levels of technology, complexity and service requirements differently. At level one, OEMs require standard assemblies based […]

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Printed Circuit Design & Fab: Design Practices for Panelization and Depanelization

Panelization, also known as the processing of boards in an array format, keeps small boards attached to each other within a single, larger substrate. Panelization is used to process multiple small boards through assembly, and is becoming more prevalent as board sizes shrink. There are two primary reasons for using an array scheme: One is […]

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PCD&F: Using Forensics to Improve PCB Design and Assembly

X-ray and AOI, along with related equipment, have long been the stalwarts of post-placement printed circuit board inspection. Over the years, as packaging, device and board technologies have advanced, these inspection technologies have advanced as well to present the best inspection results possible based on the technology of the day. These inspection machines are nondestructive, […]

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Stepping Out With 0.4mm Pitch BGA/PoPs

Package-on-package is a method of stacking components atop one another. Some OEMs use PoP to reduce the board real estate area, particularly for small handheld products and devices. Others are moving to PoP because end-markets demand greater performance in smaller systems and products. In either case, OEMs will find that there‚Äôs a game changer going […]

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Smoothing the Layout to Test Flow

Putting these two under one roof provides OEMs greater assurances the end-product is successfully tested and avoids unforeseen problems. PCB layout and test are inextricably intertwined. Some contract manufacturers maintain an in-house staff of layout designers, as well as assembly/test engineers. In such cases, the layout engineer delays creating all the necessary test points to […]

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Considerations for Proper Layout of a High-Speed PCB

A review of the signal integrity demands of digital and analog components. An endless variety of software tools exist to ensure signal integrity at the board level. The critical tool, however, is careful evaluation of considerations to maintain PCB signal integrity. Take the power supply, for example. A misstep or two here can have adverse […]

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Procurement ‘Trio’ Poses OEM Issues

A sharp procurement eye must be constantly cast on innumerable potential pitfalls. With PCB Procurement come two extremes you can hardly escape: the new component and the old. And right in the middle are those components not designed in the US. All three scenarios pose challenges and potential pitfalls for OEMs. It’s important to clearly […]

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New Materials and Techniques Tackle PCB Thermal Management

Chipmakers do their part. But at the printed circuit board level, using the right mix of old and new materials effectively ushers out increasing heat. New thermal management materials and techniques are being applied to subsystem PCB designs to meet heat dissipation demands introduced by new generations of mostly analog and some digital ICs that […]

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Improving Fabrication Yields

How the CAM engineer can make the difference. Embedded in fabrication planning is calculating panel size, checking layer stackup information, reviewing expected yields, reviewing board construction and verifying impedance control calculations. Typical panel sizes are 9 x 12″, 12 x 18″, 18 x 24″, or 18 x 36″. A number of factors need to be […]

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Managing Crosstalk and Ground Bounce

Designing for higher speeds and operating frequencies demands close scrutiny to minimize the effects of unwanted energy transfer and noise in the system. With faster edge rates of logic devices more common, wavelengths are becoming comparable to the average circuit size. As a result, the semiconductor industry is being pushed to the limits of miniaturized […]

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