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Thermal Management and Power Integrity in Tight Spaces

PCB thermal management has traditionally been seen as secondary to signal integrity. But due to tremendous evolution of power densities in transistors, PCB thermal management has now become a serious issue that must be considered early in the design.

by Syed W. Ali, Nexlogic

The advent of programmable logic devices (PLDs) increased circuit component miniaturization and increasing circuit densities on PCBs have introduced an exponential increase in power densities. Usually PCB thermal management is considered as secondary to signal integrity or power management. However, this task can no longer be ignored. If ample amount of work is not done at the layout level, and heat sinking techniques are not employed, heat generated by devices can result in parasitic effects to the circuit performance along with the reduced reliability and lifetime of the product.

Failure rate or mean time between failures (MTBF) measures component reliability. According to the Arrhenius equation, every 10°C rise in temperature above the component’s maximum operating temperature can increase the failure rate by as much as 50%. Hence the reliability or life expectancy of a component is related to its operating temperature. Additionally, above certain temperatures, a component can be irreversibly destroyed. The task of thermal management is to make sure that electronic assemblies are maintained below the maximum rated temperatures of all the components. Maximum operating temperatures of typical components are 85°-125°C for capacitors and 125°-175°C for integrated circuits.

Secondly, self-heating can adversely affect device performance. The value of output voltages and the references of certain logic families can be affected by changes in junction temperatures. Such changes, if drastic, can alter the voltage levels. The logic family that experiences a significant effect is the emitter-coupled logic (ECL). It has also been noted that thermal offsets can trigger unhealthy effects on the performance of high power microwave transistors. This is due to the fact that under high power conditions, device lattice temperature increases. This causes a drop in carrier mobility thereby negatively affecting device performance.

PCB Thermal Management

The first stage of thermal management is at the IC design level. Unfortunately, design engineers and layout designers have little or no power at this stage. Hence, it behooves the chip designer to consider any IC hotspots at design stage.

The circuit design level is the second stage of thermal management. The design engineer can take into account thermal characteristics of the circuit. For example, when designing the matching networks of power amplifiers, they can choose to implement harmonic tuning, which can reduce the amplifier’s operating temperatures. The downside of this method is that it may increase the circuit complexity.

The third stage is the layout level for which both the design engineer and the PCB designers areresponsible. It’s in the best interest of the design engineer to identify PCB hotspots that need to be communicated to the designer, who in turn will use good layout practices with PCB thermal performance in mind.

There are three mechanisms by which heat can be transferred away from the power dissipating devices: conduction, convection and radiation. Conduction is the primary means by which heat can be transferred through a solid, which in this case is the PCB. Heat transferred by conduction is directly proportional to the cross-sectional area of the material and inversely proportional to the thickness of the material. Convection involves the transfer of heat between the solid and fluid, which in this case would be the PCB or component body and air. The rate of transfer is primarily a function of exposed surface area of the solid and the temperature gradient between the solid and the fluid. Radiation involves the transfer of heat as electromagnetic radiation, which does not require a medium to travel. The rate of this transfer depends on the surface area of the solid and the temperature. Standard PCB materials like FR-4 have low thermal conductivity, hence copper will usually dominate the heat flow on the PCB.

Layout Guidelines for Thermal Management

Certain procedures must be employed during the layout stage and in fact should be used as a standard practice while laying out boards with tight spaces with due regard for thermal performance. The designer should start with the power section of the board.The reasons are that switching power supplies are noisy and their thermal management can be challenging. That’s because power dissipating components need to be close to each other for electromagnetic compatibility (EMC) purposes and space constraints. A balance is required between too close for thermal reasons and too far for EMC reasons. It is always a good practice to have some distance between switching transistors and bulk electrolytic capacitors. One method that the designer would use to reduce power supply temperature is to create large areas of copper with the power supply circuitry.

This method does work some of the time, but overestimating the amount of copper required can be both ineffective as well as detrimental to circuit performance because it contributes to electro-magnetic interference (EMI). Remember that perfect thermal conduction requires not only an ample surface area, but also a heat sink that is thick enough to radiate enough heat away. Unfortunately PCB copper is not thick enough for perfect conduction. Hence at some point just increasing the area results in diminished returns. Typically, for 1 ounce of copper, a copper area of more than 1 square inch will not give reasonable results. If space of about 3 square inches is available, then the ideal copper weight would be 2 ounces or more. Figure 1 shows a triple switching power supply layout. Note that the copper weight used in this case was 2 ounces.

Once the power layout is complete, and all the critical mechanical issues have been dealt with, the layout designer should start with the placement of the critical power dissipating devices. To avoid clustering the hot components on the PCB, power dissipating devices should be distributed across the PCB and positioned close to heat sinks. This step is very important for tightly packed boards.

After these critical components have been placed, heat sinking guidelines associated with all leaded and non-leaded devices like the ball grid arrays (BGAs), quad flat packs (QFPs) and quad flat no-leads (QFNs) must be followed. BGAs are relatively better in terms of thermal performance when compared to other types of devices because they allow for airflow beneath the device and can perform well when coupled with fan cooling methods. Figure 2 shows one side of the BGA as seen under a microscope.

RF power devices typically generate heat that must be conducted away from the device through its central pad. Generally housed in QFP or QFN packages, such devices have a row of perimeter pads around a larger central PAD encapsulated in a plastic body.

The pad lowers the thermal resistance of the package. The device runs cooler, which translates into higher reliability. The device center pad works both ways as the device ground as well as the primary conduction path to remove the package heat. The advantage of having the center pad at 0 potential is that large copper planes will not contribute to EMI.

During the layout of such devices, the thermal pad on the PCB should ideally be created as the same size as the spreader underneath the package. This will help the device to self-center during reflow. Secondly, the device central pad requires an extensive thermal via structure that can route the heat out to the cooler regions of the PCB. The drill size of the thermal vias should ideally be below 0.3 mm. This will allow it to be completely filled during reflow. Filled vias help in two ways. The vias will efficiently conduct heat to the other side, and the vias will not starve the thermal pad of solder and pull down on the device, which may have detrimental effect on the device assembly. Figure 3 shows a cross-section of a typical QFN package mounted on a PCB.

It is a good idea to use as many vias as possible placed on a 25 mil grid on the thermal pad. These vias can be connected to internal ground planes, or better yet, to an exposed pad on the other side of the board, to draw the maximum amount of heat. Use of thermal vias along with the thermal pad can increase heat dissipation by as much as 70%. Such vias act like thermal shunts. A typical layout of QFN is shown in Figure 4.

If the steps mentioned above are not adequate to keep the junction temperatures of components below their rated values, then heat sinks need to be employed. In fact, most of the time the use of a heat sink is the most effective method of thermal management. The optimization criterion is to minimize the exposed heat exchanger’s surface area while minimizing the weight of the heat sink and distance from the component to be cooled.

Heat sinks are made of thermally high conductive materials like copper or aluminum. Increasing their surface area by the use of fins removes the heat to the ambient. The interface between heat sink and the device is also important for efficient heat transfer. The connecting surfaces should be as even as possible and they should be attached by using a high conductive grease or elastomer (Figure 5).

Finally, the use of ground planes helps in a lot of ways including improved PCB thermal performance. Ground planes help get returns directly underneath their signals, which becomes mandatory at higher frequencies, and they provide a capacitive link to noisy signals and hence aid in crosstalk issues.

The PCB must be designed so that all the semiconductor devices on board are maintained at or below their maximum rated temperature. Thermal management can sometimes be problematic for dense boards employing fine pitch devices. But if certain layout guidelines are not followed and due considerations are not given to the PCB’s thermal performance, one can end up with a product that has sub-par performance and reliability in the field.

Nexlogic Technologies, San Jose, CA. (408) 436-8150. [nexlogic.com]